1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a structure of and a method of producing an MISFET.
2. Description of the Related Art
In an MISFET and a method of producing it, in order to reduce the gate length of the MISFET while suppressing a short channel effect (a phenomenon where, as the gate length becomes short, the threshold voltage drops or the device is prevented from entering a non-conducting condition), the depth of the source and drain region should be reduced substantially in proportion to the gate length.
Normally, a source and drain region of an MISFET is formed by implanting an impurity into a substrate by ion implantation and then heating the substrate to electrically activate the impurity (so that the impurity enters into site positions of the substrate crystal). In this instance, in order to make the thickness of a diffusion layer of the source and drain region shallow, either the energy of ion implantation is reduced to reduce the implantation range of the ions or the annealing time is reduced, or the processing temperature is lowered to suppress diffusion of the impurity. With the ion implantation described above, however, a channeling phenomenon occurs wherein the impurity profile trails the end in the depthwise direction toward a particular crystal orientation in which the collision probability with atoms of the substrate is low. Particularly, this phenomenon occurs remarkably with atoms having a small mass number such as boron atoms. Further, for electric activation of the impurity, unrestricted reduction of the annealing time or unrestricted lowering of the processing temperature is not an option. For these reasons, realization of a shallow junction required by submicron devices is increasingly difficult.
Further, even if a shallow junction is realized with an MISFET, the MISFET still has a problem of the parasitic resistance. In particular, as the reduction of the MISFET proceeds, the resistance of the channel portion of the MISFET device decreases. Conversely, the parasitic resistance of the source and drain region tends to increase because the depth thereof decreases. Therefore, although the performance of the intrinsic device is improved, the performance of the entire device is suppressed by the parasitic resistance, and this greatly reduces the advantage of size reduction very much.
Thus, in order to realize a reduced MISFET, it is required that the source and drain diffusion layer be formed with a small depth and a low resistance. As a means of achieving for this, a device structure wherein the source and drain region is elevated with respect to the substrate has conventionally been examined. A method of producing such a structure is disclosed in IEDM Technical Digest, 1987, pp.590-593. FIGS. 1(a) to 1(c) are sectional views illustrating successive steps of the method of producing a reduced p-channel MOSFET disclosed in this paper. The prior art disclosed in the paper is hereinafter referred to as the first prior art.
Referring to FIG. 1(a), isolation 22 is first formed on the surface of silicon substrate 21, and then gate insulator 23 and gate electrode 24 are successively formed. Further, cap insulator 25 is formed on gate electrode 24. Thereafter, low concentration diffusion layer 26 is formed. Here, the formation of low concentration diffusion layer 26 is performed by ion implantation of boron, and the impurity concentration is adjusted to approximately 10.sup.18 atoms/cm.sup.3.
Then, sidewall insulator 27 for covering a sidewall of gate electrode 24 is formed as shown in FIG. 1(b). The film thickness of a sidewall insulator 27 is approximately 100 nm. Thereafter, elevated source and drain 28 is formed on low concentration diffusion layer 26 described above. This elevated source and drain 28 is formed by selective growth of silicon single crystal. Then, an impurity of boron is implanted into the selectively formed elevated source and drain 28, and then annealing for activation is performed. In this instance, for the ion implantation, a method wherein boron is, so that the end of the implanted boron region may reach the inside of the semiconductor substrate, or another method, wherein boron is implanted so that almost all of it is contained in the elevated source and drain 28 and is then diffused into the substrate by subsequent annealing, may be available. However, since the diffusion increases the end trailing phenomenon of the impurity profile compared with that in its initial condition, the former method is preferably employed for the production method.
A p-channel MOSFET having elevated source and drain diffusion layer 28A as shown in FIG. 1(c) is formed in such a manner as described above. Here, the diffusion layer of the source and drain region of the MOSFET has a structure (hereinafter referred to as LDD structure) which has a region of a low impurity concentration (normally called lightly doped drain region) and another region of a high impurity concentration.
A method of forming a source and drain region different from the first prior art described above is disclosed in IEDM Technical Digest, 1992, pp.853-856. FIGS. 2(a) and 2(b) are sectional views illustrating successive steps of the method of producing a reduced n-channel MOSFET disclosed in the paper just mentioned. This prior art is hereinafter referred to as the second prior art.
Referring to FIG. 2(a), isolation 32 is first formed on the surface of silicon substrate 31 and then gate insulator 33, gate electrode 34, cap insulator 35 and sidewall insulator 36 are successively formed. Thereafter, elevated source and drain 37 is formed. Here, elevated source and drain 37 is formed by selective growth of a silicon single crystal. Further, facet 38 is formed at a location where elevated source and drain 37 contacts with sidewall insulator 36, and a lower face 38' closely contacts with the gate sidewall insulator.
Then, ion implantation of phosphor into elevated source and drain 37 is performed, and then annealing is performed. Source and drain diffusion layer 37A is formed in this manner on elevated source and drain 37 as shown in FIG. 2(b), and source and drain junction surface 39 is formed in a portion of silicon substrate 31.
Differences of the second prior art from the first prior art will be described below except for the difference in conductive type. In particular, the first difference is that the diffusion layer of the source and drain does not have the LDD structure. Instead, however, the thickness of sidewall insulator 36 is reduced to several tens nanometers so that phosphor implanted into elevated source and drain 37 by ion implantation may reach a location below gate electrode 34 by the ion implantation and thermal diffusion. The second difference is in that facet 38 (a surface which appears during epitaxial growth and is directed in a particular crystal orientation) is formed at a portion of elevated source and drain 37 formed by the selective growth at which elevated source and drain 37 contacts with sidewall insulator 36. Due to the presence of facet 38, an increase of the parasitic capacitance between gate electrode 34 and source and drain diffusion layer 37A, when the sidewall insulator is formed thin, is suppressed.
Meanwhile, an MISFET, which employs a semiconductor selectively grown in order to obtain a junction surface of a shallow depth, and a method of producing the same are reported in SSDM Extended Abstracts, 1994, pp.999-1000. The prior art disclosed in the paper just mentioned is hereinafter referred to as third prior art. As seen in FIG. 3(a), isolation 42 is first formed on the surface of silicon substrate 41 and then gate insulator 43 and gate electrode 44 are successively formed of polysilicon. Thereafter, thermal oxides 45A and 45B are formed on the surfaces of silicon substrate 41 and gate electrode 44 by thermal oxidation. In this instance, since the rate of oxidation is different between substrate 41 and gate electrode 44, thermal oxide 45A of a greater thickness is formed on gate electrode 44. Thereafter, oxide films 45 are etched by isotropic etching, and only silicon substrate 41 is exposed while thicker thermal oxide 45A remains around gate electrode 44. Then, single crystal 46 of p-type silicon-germanium mixed crystal doped with boron is selectively grown only on the exposed surface of silicon substrate 41. By the steps described above, such a p-type MOSFET as shown in FIG. 3(b) is formed.
The first and second prior arts have a basic idea that, where the extent of the impurity after completion of the ion implantation step and the annealing step is represented by depth a and the thickness of the elevated source and drain is represented by b, b is subtracted from a to decrease the depth of the junction from the surface of the semiconductor substrate and the thickness of the source and drain region is maintained by the elevated source and drain to reduce the parasitic resistance. However, the method wherein the junction depth is determined by subtraction involves a great error of the junction depth. For example, where a=100 nm, b=50 nm and the relative error for both a and b is .+-.10%, the junction depth is a-b=50 nm and the maximum error of the junction depth is 100 nm.times.0.1+50 nm.times.0.1=15 nm, and consequently, the relative error of the junction depth (=15 nm/50 nm) amounts to .+-.30%. It is difficult to control the dispersion in relative error of the junction depth.
Further, the first and second prior arts have a common disadvantage in that, since ion implantation is employed, the concentration of the source and drain diffusion layer in the inside of the substrate cannot be raised sufficiently due to an influence of the trailing of the end of the impurity profile described above. Where the impurity concentration is represented by N and the depth is represented by x, the following equation (1) given below stands approximately at the end portion: EQU d(log.sub.10 N)/dx=C (1)
Here, if concentration N at junction depth x=x.sub.j from the surface of the semiconductor surface is placed as N.sub.j, then concentration N.sub.s at the surface of the substrate (at the lower surface of the elevated source and drain) is approximately given by the equation (2): EQU N.sub.s =N.sub.j .times.10.sup.cx j (2)
where C is a constant.
In ion implantation, the trailed end is great, or in other words, C is small. Consequently, N.sub.s does not become sufficiently high, and the resistance of a portion of the source and drain region, which is positioned below the surface of the substrate, does not exhibit a sufficiently reduced value. In the elevation structure, the resistance of the source and drain layer below the sidewall, above which there is no elevated layer, has a comparatively high rate. Therefore, reduction of the resistance of the portion of the source and drain region in the substrate is important.
The first prior art has a drawback in that the short channel effect and the magnitude of the parasitic resistance almost depend upon the structure of the LDD portion. Since the LDD portion is produced by an ordinary production method, the depth of the LDD portion cannot be reduced very much, and if only the source and drain diffusion layer of a high concentration is formed shallow, the improvement in short channel effect will be slight. Further, since the parasitic resistance of the LDD portion of a low concentration has a significant impact on the parasitic resistance of the source and drain region, the resistance reduction effect by the elevation is also small. Accordingly, the characteristic of the MISFET device exhibits little or no improvement from that of a device having an ordinary LDD structure.
The second prior art has a drawback in that, since the sidewall insulator of the gate electrode has a reduced thickness, the parasitic capacitance between the gate electrode and the source and drain region is large. In order to suppress the parasitic capacitance, a facet is utilized in the second prior art. However, the capacitance reduction effect is restricted because, in order to achieve the effect of reduction of the junction depth while ion implantation is employed, a portion (38' in FIG. 2) at which the sidewall insulator of the gate electrode and the elevated source and drain closely contact with each other must be provided. Further, in this instance, since a region which is not doped with the impurity is produced at a portion of the elevated source and drain, the resistance reduction effect is reduced.
On the other hand, with the third prior art, since ion implantation is not employed and a source and drain diffusion layer is formed by selective growth of crystal doped in advance, a junction of a shallow depth can be produced with a high degree of controllability. However, if the thickness of the selective growth layer is set to such a low value (as recited in the document, e.g. 15 nm) that the parasitic capacitance does not matter, an increase in resistance that arises from the fact that the junction depth is shallow is not suppressed sufficiently. On the contrary, if the thickness of the selective growth layer is increased, a decrease in resistance by elevation of the source and drain can be anticipated. In this instance, however, the parasitic capacitance creates a problem more serious than those of the two foregoing prior arts. In the third prior art which makes use of solid phase diffusion, the extent of the impurity in a lateral direction is small, and the distance between the selective growth layer and the gate must be set much closer (approximately 10 nm) than those in the two foregoing prior arts so that the impurity of the source and drain may reach a location below the gate. Otherwise, the driving capacity of the MISFET device is damaged remarkably. As a result, the parasitic capacitance between the diffusion source and the gate is greatly increased, and the speed of operation of the circuitry is decreased. The production method of the third prior art has another drawback in that it is difficult to form a complementary construction, that is, to integrate both n-type and p-type MISFETs on a single substrate. Where ion implantation is employed as in the prior arts 1 and 2, a complementary MOSFET can be formed readily by covering, upon ion implantation into the source and drain of one conductivity type, the region of the other conductivity type with a photoresist. However, in the third method wherein a diffusion layer doped in advance is formed, such a simple method as used in the first and second prior arts cannot be employed.